1. Field of the Invention
Example embodiments relate to a capacitor, a method of forming the same, a semiconductor device having the capacitor and a method of manufacturing the same. Other example embodiments are directed to a capacitor having an upper electrode structure including a first upper electrode and a second upper electrode, a method of forming the same, a semiconductor device having the capacitor and a method of manufacturing the same.
2. Description of the Related Art
Among semiconductor devices, a dynamic random access memory (DRAM) device may have a unit cell including one access transistor and one storage capacitor. As the DRAM device becomes more highly integrated, the capacitor dimension may be reduced. The capacitor may increase storage capacity regardless of the reduced size of the DRAM device.
The capacity of the capacitor may be represented by the following equation:C=∈0∈×(A/d)
wherein ∈0 indicates a dielectric constant in a vacuum, and ∈ indicates a dielectric constant of a dielectric layer. A represents an effective area of a lower electrode, and d indicates a thickness of the dielectric layer.
As shown in the above equation, the capacity of the capacitor may be improved by increasing the effective area of the lower electrode, reducing the thickness of the dielectric layer and/or employing relatively high dielectric material as the dielectric layer. The lower electrode of the capacitor may have a cylindrical structure that has a height larger than a width thereof, thereby increasing the capacity of the capacitor.
In a conventional method of forming a cylindrical capacitor, an insulating interlayer having a contact pad may be formed on a semiconductor substrate, and then a cylindrical lower electrode having a relatively high aspect ratio may be formed on the contact pad. After a dielectric layer is formed on the cylindrical lower electrode, an upper electrode may be formed on the dielectric layer. The upper electrode may include a polysilicon germanium layer doped with p-type impurities.
The p-type polysilicon germanium layer of the upper electrode may be directly formed on the dielectric layer without forming a seed layer so that the size of the grains in the p-type polysilicon germanium layer may be undesirably increased. Voids may be generated between the dielectric layer and the upper electrode because the p-type polysilicon germanium layer having the relatively large grains may not be properly formed on the dielectric layer. When the voids are formed between the dielectric layer and the upper electrode, electrical characteristics of the capacitor may be deteriorated.